Operation

ABSTRACT

THERE IS DESCRIBED A COMPUTER SYSTEM IN WHICH A SPECIFIC COMMAND IN A PROCESSOR SETS A FLAG BIT IN A WORD IN MEMORY AT THE TIME THE PROCESSOR READS THIS WORK OUT OF MEMORY. THE FLAG BIT THEN INDICATES, WHENEVER THAT PARTICULAR WORD IS ACCESSED IN MEMORY THAT THE WORD IS &#34;LOCKED&#34; AND MAY BE USED TO PREVENT USE OF THE WORD UNTIL THE FLAG BIT IS RESET.

Oct. 30, 1973 c. B. CARLSON Er AL Re. 27,791

DIGITAL COMPUTER WITH MEMORY LOCK OPERATION 3 Sheets-Sheet 1 OriginalFiled June '7. 1965 Oct. 30, 1973 Q B. CARLSON ET AL Re. 27,791

DIGITAL COMPUTER WITH MEMCRY LOCK OPERATION I5 Sheets-Sheet 2 OriginalFiled June '7, 1965 l I I I I I I I I I I I I I I l I I S www? 1 f\ NNmu QI o km I I I IQJ... I Iwwmmmlql v I I I| www #M M L y Wm KS, 1 n W.Q MTB Q y QS 1 kkwm @i M mm mw e I im@ Q s, W.. MW r IIJ rbJ IJ I w. QSmv M I Q o .SQ ww X QG N5 /]\I\ E NQQ I NQQ Mmm wh @M Il I n. @I .n x mN Q N QW NS NMMN xm QN I l I I I I I I l I I l I I I I I I I L I I IIIIIIIIIIIIIIIIIII I l Oct. 30, 1973 c. B. CARLSON ET AL Re. 27,791

DIGITAL COMPUTER WITH MEMORY LOCK OPERATION Original Filed June 7. 19653 Sheetsheet 5 IHIIIDIU n P-l @y ma? al n fc) w L L maf/ff n (i) n//rf n(fj/06K L United States Patent Oce Re. 27,791 Reissued Oct. 30, 197327,791 DIGITAL COMPUTER WITH MEMORY LOCK OPERATION Carl B. Carlson,Santa Barbara, Calif., and Robert V.

Bock, Malvern, Pa., assignors to Burroughs Corporation, Detroit, Mich.

Original No. 3,398,405, dated Aug. 20, 1968, Ser. No. 461,923, June 7,1965. Application for reissue Oct. 8, 1969, Ser. No. 871,491

Int. Cl. G06f 11/10, .I5/16 U.S. Cl. S40-172.5 19 Claims Matter enclosedin heavy brackets I] appears in the original patent but forms no part ofthis reissue specification; matter printed in italics indicates theadditions made by reissue.

ABSTRACT OF THE DISCLOSURE There is described a computer system in whicha specific command in a processor sets a flag bit in a word in memory atthe time the processor reads this word out of memory. The ag bit thenindicates, whenever that particular word is accessed in memory, that theword is locked and may be used to prevent use of the word until the`flag bit is reset.

This invention relates to digital computers and, more particularly, isconcerned with a lock on any data stored in main memory or anyperipheral storage apparatus used in connection with the computer.

Multi-processing or multi-programming operation of digital computersystems has been developed to take advantage of the high speed operationof processors. For example, a computer system may include severalprocessors operating with a plurality of memory modules so that the samedata may be accessed for two different programs or utilized in twodifferent processors at substantially the same time. It is possibleunder such arrange ments where a common information base is being usedfor more than one processor or in connection with more than one program,that while one piece of data is being modified, another processor, orthe same processor using another program, may access the same word inmemory to modify or use this data.

It has been the practice heretofore to provide information on the statusof a tile or array of data by programming. A group of words are setaside in memory and used to establish the status of data, such as anarray of data in the core memory or a magnetic tape file or the like. Byproper programming, the status table must always be referenced beforegoing to a file to determine if the tile is available for use with aparticular program. Thus the word in the status table operates as a keyfor locking or unlocking a le. When the word in the status tableindicates that a tile is unlocked, any program may operate on it.However, when a word in the status table is modified to indicate thatthe file is locked, only the program which established the lockedcondition can operate on that iile.

In such an arrangement, a series of program steps or instructions mustbe established by which the status table is interrogated beforeoperating on any file. If the status table indicates that the file islocked, the program instructions must be such as to delay access to thatfile and establish some alternative mode of operation for the processor.On the other hand, if this status table indicates that the file is open,the program must follow a series of instructions by which the statusword is brought out of memory, modified to indicate that the tile is nowlocked and return it to the status table in memory before accessing thedata in the file itself.

However, in multi-processing or multi-programming systems, during thetime a status word is read out of memory into the processor, examinedand then stored back in memory by the processor with the word modifiedto indicate that the corresponding file is locked, it is possible for asecond processor to read the same status word before it has beenmodified so as to lock the designated tile. Thus two programs can nowproceed to operate on the same file and the attempt to program a lockedcondition of a le through the status word table will have failed.

The present invention provides an arrangement by which during theexecution of a read-out instruction of any word from memory, the wordcan at the same time be modified in the memory to indicate that the wordor the file or array of data which it designates is locked and thereforeinaccessible to other processors or other programs.

The present invention accomplished this by providing in a digitalcomputer system a program instruction called a Read With Lock. When thisinstruction is encountered in executing a stored program in the computersystem, an access to memory is instituted. Preferably, a magnetic corememory is employed in which the binary bits forming the word are storedin magnetic form in cores. The read-out operation from a core memory isself-destructive of the information and therefore the complete readoutoperation normally requires that the word be rewritten in the coresduring the memory cycle to prevent loss of the information in thememory. When a Read With Lock instruction is encountered, according tothe teaching of the present invention, means is provided to set at leastone bit in the word when it is rewritten into the core memory incompleting the memory cycle. The next time the word is read out ofmemory the bit that is set provides a tiag to the processor that theword has been previously read out of memory. The flag bit is used toprevent any modification or further use of the word as an address to atile of data, for example, until the bit is reset by replacing the wordin memory through the normal Store instruction.

For a more complete understanding of the invention, reference should bemade to the accompanying drawings wherein:

FIG. 1 is a block diagram of a multi-processor computer systemincorporating the present invention',

FIG. 2 is a schematic block diagram showing one embodiment of thepresent invention; and

FIG, 3 is a timing diagram useful in explaining the operation of theinvention.

Referring to FIG. l, there is shown a data processing system such asdescribed in more detail in copending application Ser. No. 89,866, tiledFeb. 16, 1961, by the same assignee as the present application, now Pat.N0. 3,200,380. Such a system may include one or more processors, two ofwhich are shown by way of example and indicated at 10 and 12. Eachprocessor is arranged to communicate through a switch interlock circuit14 with any selected one of a number of memory modules such as indicatedat 16, 18 and 20. Also each processor can communicate through the switchinterlock with any one of a plurality of input-output channel controlcircuits such as indicated at 22, 24 and 26. Each input-output channelin turn may be connected to any one of a number of input-output units,such as a magnetic tape unit 28, a card reader 30 or a magnetic drum 32,for example, through an input-output exchange circuit 34. The systemoperates such that when any processor needs to communicate with a memorymodule, an address is generated within the processor which not onlyaddresses a particular word in a memory module but also designates whichof the plurality of memory modules is to be used. The address controlsthe switch interlock 14 to connect the selected memory module to theprocessor during a memory cycle in which a word is transferred frommemory to the processor or from the processor to the memory.

When information is required from a peripheral unit such as the magnetictape unit 28, a word is generated in the processor known as aDescriptor. A Descriptor is transferred to one of the input-outputchannels where it is used to control the transfer between a designatedterminal unit such as a magnetic tape transport 28 and a designated oneof the memory modules.

In a data processing system such as that shown in FIG. 1 and describedmore fully in the above-identied copending application, it is possiblefor both processors l and 12 to access the same information in aparticular memory module or a particular peripheral unit. As pointed outabove, a problem may arise where one processor may be modifying dataunder one program and the same data is accessed by another program. Thepresent invention provides a special program instruction which permits aparticular word in a memory module to be transferred to a processor andat the same time that word be locked so that it cannot be used by theother processor or by a different program with the same processor. Themanner in which this Read With Lock instruction is implemented in thedata processing system of FIG. l is described in detail in connectionwith FIG. 2.

The processor is shown as including a program register 40 which storeseach instruction comprising the program for the processor. Eachinstruction is transferred into the program register 40 from a programstored in a memory module in a manner described in more detail incopending application Ser. No. 242,002, led Dec. 3, 1962, and assignedto the same assignee as the present application. Instructions generallyare of two types, one of which calls for some arithmetic operation andthe other of which calls for a memory access operation either forreading words from a selected memory module into the processor orwriting words from the processor into the memory module. Instructionswhich call for an arithmetic operation utilize operands stored in anA-register 42 and a B-register 44. Instructions of this type are notpertinent to the present invention except to note that operands mustfirst be placed in the A-register 42 and the B-register 44 from a memorymodule, such as the module 16, in response to a previous Memory Readinstruction such as a Memory Read With Lock instruction.

Assuming that a Read With Lock instruction has been loaded in theprogram register 40, a timing unit 46 decodes the instruction andgenerates a sequence of timing signals which control the processor toeffect the transfer of a word from a memory module to the processor.

The address necessary to do a memory operation is stored in either oftwo registers, designated the M-register 48 and S-register 50. Bothregisters are in the form of counters which can be counted in responseto signals from the timing unit 46.

As described in more detail in application Ser. No. 242,- 002, tiledDecember 3, 1962, and assigned to the same assignee as the presentapplication, when the instruction in the program register 40 calls for amemory access, the timing unit 46 decodes the instruction in theregister 40 and provides timing signals to a control circuit 56. Thetiming signals applied to the control circuit specify whether a read orwrite operation is to take place in the memory unit 16 and designatewhether the address contained in the M-register 48 or the S-register 50is to be used in addressing the memory unit 16. The timing signals alsodesignate which one of the A and B-reigsters 42 and 44 is to be used forthe transfer of a word of information between the processor 10 and thememory unit 16.

The control circuit 56 contains an E-register 58. The E-register 58 isset into a unique state by the timing signals provided by the timingunit 46 and thereby provides a stored indication of the memory accessoperation which is to be performed. For the Read With Lock instruction,the E-register 58 is set to initiate a memory read operation using theaddress in the M-register 48 and transferring the word from memory toeither the A-register 42 or the B-register 44.

The E-register 58 is set for a memory read operation and through a gatecontrol circuit 60 controls a gate 62 or 64. The address in either theM-register 48 or the S- register 50 is thereby gated by a logical ORcircuit 66 to the memory unit 16 through the switch interlock 14. Theswitch interlock is shown schematically as a series of switches by meansof which connections are completed between the processor 10 and theparticular memory unit 16. At the same time, a signal from the timingunit 46, which is set by the decoder in the timing unit 46 when a ReadWith Lock instruction is provided in the program register 40, is appliedto a logical AND circuit 68 together with an output line from theE-register 58, indicating that a memory read cycle is being initiated.The output of the logical AND circuit 68 is also connected through theswitch interlock 14 to the memory unit 16.

The interlock circuit 14 includes a decoder 70 coupled to the output ofthe logical OR circuit 66. The decoder, in response to an address beinggated into the memory unit 16, energizes a control line RL which signalsthe memory unit 16 that a memory access is being made to the particularmemory unit. In addition, a line from the E-register 58 is energizedwhen a memory write cycle is to take place but is not energized when amemory read cycle is taking place. For the purpose of the presentdiscussion, we are only concerned with a memory read operation and so nosignal need be provided on the write line.

The memory unit 16 includes a conventional coincident current type ofmagnetic core memory unit 72. An address register 74 stores the addressinformation derived from the processor by which a word is selected inthe core memory 72 to be read out into an information register 76.Read-out from the core memory 72 takes place in response to a pulseapplied to the core memory from a logical AND circuit 78 through a groupof output arnpliers 80. Since core memories involve a destructive readout, the information is restored in the same address in the core memoryby a plurality of driver amplifiers 82 controlled in response to the bitstored in the information register 76 by a write pulse derived from theoutput of a logical AND circuit 84.

Operation of the memory unit in performing a memory cycle is controlledby a memory counter 86. An output signal on the line RL from the decoder70 is applied to an AND circuit together with the initial state of thememory counter 86, designated t0, and a clock pulse. Thus when theoutput of the decoder 70 indicates that a memory cycle is to beinitiated, the output of the AND circuit 88 is used to advance thememory counter into the t, state.

At the same time the output of the AND circuit 88 strobes a pair ofgates 89 and 91 for loading the address register 74 from the M-registeror S-register and for loading the information register, in the case of amemory write Operation, from the A-register er B-register,

The t1 state of the memory counter 86 is applied to the AND circuit 78together with a clock pulse which is delayed a fraction of a clock pulseinterval by a delay circuit 90. This is shown in the timing diagram ofFIG. 3 which shows at (A) the signal on the line RL which exists for oneclock pulse interval and corresponds to the to state of the memorycounter 86. The memory counter 86 changes to the t, state with the nextclock pulse, at which time the memory counter 86 changes to the t2state.

The waveform (B) of FIG. 3 shows the delay pulse at the output of theAND circuit 78. This pulse is applied to the core memory 72 causing aread out of the word selected by the address register 74. The word isamplified by the readout amplifiers 30 and coupled to the informationregister 76 through a logical OR circuit 92, and an inhibit gate 94. Theinhibit gate 94 is controlled by a flip-flop 96. The flip-flop 96 isnormally in the 0 or ofi condition when a memory read operation is totake place and is set in the 1 or on condition by the Write line fromthe E-register 58. Thus the gate 94 applies the word read out of thememory 72 into the register 76 for a memory read cycle but inhibits thetransfer of the Word during a memory write cycle. The signal from theliip-op 96 as applied to the gate 94 is shown in FlG. 3(C).

The word stored in the information register 76 is transferred to theA-register 42 or the B-register 44 by means of a gating circuit 98 inthe memory module 16. The gating circuit 98 is strobed by a clock pulseat the end of the t1 state of the memory counter 86 by means of an ANDcircuit 97 to which is applied the t! state and the Read level from theflip-flop 96. The strobe pulse at the output of the AND circuit 97transfers the word in the information register 76 through the switchinterlock 14 to the A-register 42 or B-register 44 through gate 99 orgate 101 as determined by the gate control circuit 60.

When the memory counter 86 advances to the t3 state, the next clockpulse is passed by the AND circuit 84 and is used to strobe the driveramplifiers 82 by which the word stored in the information register 76 isrewritten back in the same address location of the core memory 72.During the t., and t5 states, the memory module is returned to itsinitial condition by resetting of various logic fiip-flops and the like,as described in more detail in the above-identied patent applicationSer. No. 242,002.

When a Read With Lock operation is to take place in accordance with theteaching of the present invention, as pointed out above, a signal isprovided at the output of the AND circuit 68 which is applied to thememory module 16. The lock signal, the Waveform being shown in FIG.3(F), is applied to a logical AND circuit 100 and a logical AND circuit102. The logical AND circuit 100 also receives a clock pulse and the t2level from the memory counter 86. The output of the AND circuit 100 is apulse occurring at the end of the t2 state of the memory counter 86 andis used to set one flip-nop in the register 76 to the on" or l state.The corresponding bit in the word stored in the information register isthereby set to indicate that the word has just been accessed from thememory 72 and is being transferred to a processor. The AND circuit 102also senses that the memory counter 86 is in the t2 state and that aRead With Lock operation is taking place and also senses that theinformation register flip-flop controlled by the AND circuit 100 is inits 0 state. If all conditions are true, the output of the AND circuit102 complements the flip-flop in the information register 76 whichcontains the parity bit. In this way, the parity is corrected at thesame time the bit indicating a Lock condition is set by the output ofthe AND circuit 100. If the Lock bit had already been set to l during aprevious memory cycle, no complementing would take place and the paritybit would remain the same.

By setting the Lock bit in the word stored in the information register76 before it is rewritten in the core memory 72, a flag signal isprovided which on any subsequent memory access of the same word, givesan indication of the previous access to that same word. Since this Hagis automatically set during one memory cycle, there is no way the sameword can be accessed by two processors without the flag being set by thefirst processor to access the word.

When a word is transferred to the A-register 42 or B-register 44, theLock bit is sensed and applied through a logical OR circuit 104 to analarm 106, for example. The same signal may also be applied to thetiming unit 46 to interrupt or modify the operation of the processorwhen a locked word has been accessed from memory.

From the above description, it will be recognized that the presentinvention provides means for flagging that a word in memory haspreviously been accessed. The word may be a status word providingaddress information to a file of data, such as a Descriptor word. Thelocked condition may be subsequently removed by using a conventionalStore instruction in which the word is again stored in memory in itsoriginal unlocked condition.

What is claimed is:

1. A digital computer system comprising a rst register for storingprogram words, a second register for storing memory address words, athird register for storing operand words, an addressable storagefacility for storing a plurality of words, means responsive to apredetermined program word in the first register and the address word inthe second register for transferring a selected word from the memoryfacility to the third register, means operatively associated with thestorage facility for setting a predetermined bit of any word addressedin the storage facility to one binary value, and means responsive tosaid predetermined word in the first register for actuating said bitsetting means to modify the addressed word after the addressed word istransferred from the storage facility to the third register, whereby theWord is received in the third register in unmodified form but the wordis modified as stored in the storage facility.

2. Apparatus as defined in claim 1 including means operativelyassociated with the storage facility for changing a second bit in theword when said first bit is set by said bit setting means.

3. In a computer system having a plurality of digital processors eachadapted to access a common addressable storage facility, the improvementcomprising means including a register associated with the addressablestorage facility for transferring a selected Word from an addressablelocation into the register, means for transferring a word from theregister to a selected location in the storage facility, meansresponsive to a first signal from one of said processors for loadingsaid register from a selected location in the storage facility andtransferring said word from the register to the processor, meansresponsive to a second signal from said one of the processors formodifying at least one bit in said register and initiating transfer ofsaid modified word by said transferring means into the same selectedlocation in the storage facility, and means in each of the processorssensing at least one bit in a word transferred from the storage facilityto the processor for indicating to the processor that the word has beenmodi- 4. In a computer system having at least one processor adapted toaccess an addressable storage facility, the improvement comprising meansincluding a register associated with the addressable storage facilityfor transferring a selected word from an addressable location into theregister, means for transferring a word from the register to a selectedlocation in the storage facility, means responsive to a first signalfrom said processor for loading said register from a selected locationin the storage facility and transferring said word from the register tothe processor, means responsive to a second signal from the processorfor modifying at least one bit in said register and initiating transferof said modified word by said transferring means into the same selectedlocation in the storage facility, and means in the processor sensing atleast one bit in a word transferred from the storage facility to theprocessor for indicating to the processor that the word has beenmodified.

5. A computer system comprising at least one addressable storagefacility and at least one digital processor, the storage facilityincluding an address register, an information register, and meansresponsive to a first signal from the processor for transferring a wordfrom the address location in the storage facility designated by theaddress register to the information register and back into the sameaddress location in the storage facility, means controlled by theprocessor for transferring the word in the information register to theprocessor, means responsive to a second signal from the processor forsetting at least one bit to a predetermined binary value in theinformation register, timing means for actuating the bit setting meansin response to said second signal after the word in the informationregister is transferred to the processor and before the word in theinformation register is transfered into the same addess in the storagefacility, and means for sensing and indicating that said one bit hasbeen set in any word received by the processor from the storagefacility.

6. A computer system comprising at least one addressable storagefacility and at least one digital processor, the storage facilityincluding an address register, an information register, and meansresponsive to a first signal from the processor for transferring a wordfrom the address location in the storage facility designated by theaddress register to the information register and back into the sameaddress location in the storage facility, means controlled by theprocessor for transferring the word in the information register to theprocessor, means responsive to a second signal from the processor forsetting at least one bit to a predetermined binary value in theinformation register, and timing means for actuating the bit settingmeans in response to said second signal after the word in theinformation register is transferred to the processor and before the wordin the information register is transferred into the same address in thestorage facility.

7. In a computer in which coded words forming a stored program ofinstructions are read out from storage into a program control registerand executed by a control circuit in a predetermined sequence, apparatuscomprising a core memory unit for storing a plurality of digitally codedwords in addressable storage locations including means for destructivelyreading out a selected word from the core memory unit into a registerand means for rewriting the word back into the same location in memoryto restore the word during one complete memory cycle, means responsiveto a predetermined program word in the program control register forinitiating a memory cycle, and means responsive to said predeterminedprogram word for setting one bit in the selected word read out of thecore memory unit as it is rewritten back in the core memory unit duringthe same memory cycle.

8. In a computer in which coded words forming a stored program ofinstructions are read out from storage into a program control registerand executed by a control circuit in a predetermined sequence, apparatuscomprising a memory unit for storing a plurality of digitally codedwords in addressable storage locations including means for reading out aselected word from the memory unit into a register and means forrewriting the word back into the same location in memory to restore theword during one complete memory cycle, means responsive to apredetermined program word in the program control register forinitiating a memory cycle, and means responsive to said predeterminedprogram word for setting one bit in the selected word read out of thememory unit as it is rewritten back in the memory unit during the samememory cycle,

9. In a data processing system including a storage, a storage accesscontrol, comprising:

a registering apparatus having binary register locations capable ofstoring data manifestations in the form of different bit configurationsrepresenting corresponding dierent values;

means for accessing said register locations so as to derive dotamanifestations therefrom;

and forcing means operative, directly as a result of an access by saidmeans for accessing and independently from the contents of said registerlocations, to set a pre-established bit congurntion in said registerlocations, said pre-established bit configuration identifying theaccessibility of said storage.

10. The device described in claim 9 wherein all of the bits in saidpre-established bit configuration are of the same value.

ll. The device described in claim 9 wherein said forcing means for thesetting of said pre-established bit configuration operates so as toprovide said setting prior to the possibility of any further accessingof said register locations.

12. The device described in claim l0 wherein said bits are set to allONEs.

13. The device described in claim I0 wherein said bits are set to allZEROs.

14. The device described in claim 9 wherein said forcing means includesmeans for selectively modifying the output of the memory dota register.

15. In a data processing system including a storage, a storage accesscontrol comprising:

a registering apparatus having register locations capable of storingdata manifestations in the form of different bit configurationsrepresenting corresponddifj'erent values;

means for accessing said register locations so as to derive datamanifestations therefrom;

forcing means operative to set a pre-established bit configuration insaid register locations, said preestablished bit configurationidentifying the accessi'- bility of said storage;

and means to test the data significance of the data manifestationsderived from said register locations.

I6. The device described in claim` l2 wherein only a portion of the datamanifestations of said register locations is tested for controlsignificance.

I7. In a data processing system including a plurality of storage unitsand a plurality 0f processing units, an apparatus for controllingprocessing unit access to the storage units comprising.'

a plurality of registers where each storage unit is associated with adifferent one of said registers and where each register includesregister locations capable of storing different data manifestations inthe form of dierent bit configurations;

accessing means, controlled by each processing unit, for accessing anyof said registers so as to derive accessed data manifestations from anaccessed register;

forcing means operative, directly as a result of an access by saidaccessing means and independently from the contents of said accessedregister, to set a pre-established bit configuration in said accessedregister which identifies an accessibility condition of a storage unitassociated with said accessed register;

and means controlled by each processing unit to test said accessed datamanifestations so as to determine the accessibility of the storage unitassociated with said accessed register.

I8. The data processing system of claim I4 further including resettingmeans for resetting said accessed register with a bit configurationwhich identifies another accessibility condition of the storage unitassociated with said accessed register.l

19. In a data processing system including a storage unit and aprocessing unit, an apparatus for controlling processing unit access tothe storage unit comprising.'

a plurality of registers where portions 0f each storage unit areassociated with a dierent one of said registers and where each registerincludes register locations capable of storing dierent datamanifestations in the form of different bit configurations;

accessing means, controlled by a processing unit, for accessing any ofsaid registers so as to derive accessed data manifestations from anaccessed register;

forcing means operative, directly as a result of an access by saidaccessing means and independently from the contents of said accessedregister, to set a pre-established bit configuration in said accessedregister which identifies an accessibility condition of References CitedThe following references, cited by the Examiner, are 1() of record inthe patented le of this patent or the original patent.

UNITED STATES PATENTS 3,108,257 10/1963 Buchholz 340-1725 3,158,84411/1964 Bowdle S40-172.5 l5 3,264,615 8/1966 Case et al. 340-172.53,317,898 5/1967 Hellerman S40-172.5

GARETH D. SHAW, Primary Examiner

